Home News Updates IIT Kanpur and Silizium Circuits jointly bag MeitY’s Grant-in-Aid project for Chips to Startup (C2S) program

IIT Kanpur and Silizium Circuits jointly bag MeitY’s Grant-in-Aid project for Chips to Startup (C2S) program

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The Indian Institute of Technology (IIT) Kanpur jointly with Silizium Circuits Private Limited has bagged a Rs 5 crore Grant-in-Aid project from the Ministry of Electronics and Information Technology (MeitY)’s Chips to Startup (C2S) program for its ground-breaking project, Radio-frequency (RF) Transceiver SoC (System on Chip) with integrated RISC V core for Sub-GHz Applications”.

The project duration is 3 years and IIT Kanpur as the nodal agency will be responsible for the developing of significant mixed signal IPs and Silizium Circuits will design the RF Front End and System-On-Chip (SoC) along with commercialization.

IIT Kanpur and Silizium Circuits consider this project as a pivotal point in the India’s Semiconductor ambitions. Although Indian engineers contribute significantly to the Microelectronics, most of activities were limited in service sectors. The ecosystem has undergone significant changes with many startups in this field with the support of MEITY R&D grants and DLI scheme.

Prof Abhay Karandikar, Director IIT Kanpur said, “The project, that aims at the formulation of an SoC supporting all the prominent standards in sub GHz, will drive innovations in the IoT and indoor applications. The development has tremendous market size and will put India in a stronger position with respect to a complex SoC research and development.”

Rijin John, Co-founder and CEO Silizium Circuits said “Semiconductor IPs (Intellectual Property) will be the brain of all hardware devices. Such an SoC supporting all prominent standards in sub GHz will drive innovations in the IoT and indoor applications whose revenues are forecast to be around $1.3 trillion by 2030. In addition to the final SoC, the IPs such as ADCs (Analog to Digital Convertors), PLL (Phase Locked Loops) and RF front end will also be developed which can target another $488 billion global market.  All the low-power applications worldwide in future will require an ultra-low power receiver since it has to be alert to an incoming signal at all times.”

Dr. Arun Ashok, Co-founder and CTO explains “The developed SoC will have an RF front end capable of transmitting in sub-1GHz UHF frequencies and will be compatible with various standards like LoRa, 802.15.4 WLAN, ZigBee, WiSUN and also supports modulation formats like FSK/ MSK/ 4-FSK/ GFSK/GMSK/ ASK/ FSK/ FM / PSK hence forming the backbone of most of the long, short-range, wide and narrowband communications. Together with the RF front end, the designed SoC will also house an indigenous RISC-V core powered with SHAKTI/VEGA processor enabling support of a multitude of modulation formats for the above-mentioned standards.”

Prof Imon Mondal, Prof Chithra and Prof R. S. Ashwin Kumar from IIT Kanpur and Dr Arun Ashok and Mr. Rijin John from  Silizium Circuits are the investigators of this project. The project is backed by the end-user ATWIC R&D which is an innovative establishment focused on developing electronics systems and subsystems.

Prof Imon Mondal, Department of Electrical Engineering, IIT Kanpur said, “This SoC is positioned uniquely to address the needs of several wireless segments and applications such as Sub-GHz WiFi, Narrowband IoT, Electric meters, and Secure wireless Infrastructure, besides being a critical aspect of secure wireless infrastructure.”

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